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64Mb SDRAM
Ordering Information
EM 48 4M 16 4 4 V T A - 55 L
EOREX Memory
EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM
: : : : : :
40 41 42 43 46 48
Power Blank : Standard L : Low power I : Industrial F: PB free package
Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K
Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz )
Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank
Revision A : 1st B : 2nd C : 3rd D :4th
Interface V: 3.3V R: 2.5V
Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP )
Rev.02
1/18
64Mb SDRAM
64Mb ( 4Banks ) Synchronous DRAM
EM484M1644VTA (4Mx16)
Description
The EM484M1644VTA, is Synchronous Dynamic Random Access Memory (SDRAM) organized as 1,048,576 words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 64Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL .
Feature
* Fully * Single
synchronous to positive clock edge 3.3V +/- 0.3V power supply * LVTTL compatible with multiplexed address * Programmable Burst Length (B/ L) - 1,2,4,8 or full page * Programmable CAS Latency (C/ L) - 2 or 3 * Data Mask (DQM) for Read / Write masking * Programmable wrap sequence - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ) * Burst read with single-bit write operation * All inputs are sampled at the rising edge of the system clock. * Auto refresh and self refresh * 4,096 refresh cycles / 64ms
* EOREX reserves the right to change products or specification without notice.
Rev.02
2/18
64Mb SDRAM
Pin Assignment ( Top View )
x16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
54pin TSOP-II (400mil x 875mil) (0.8mm Pin pitch)
Rev.02
3/18
64Mb SDRAM
Pin Descriptions ( Simplified )
Pin
CLK /CS CKE
Name
System Clock Chip select Clock Enable
Pin Function
Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when "H" and deactivates when "L". CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA(CA0 to CA7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged.
A0 ~ A11
Address
BA0, BA1
Bank Address
Selects which bank is to be active.
/RAS
Row address strobe
Latches Row Addresses on the positive rising edge of the CLK with /RAS "L". Enables row access & pre-charge. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access.
/CAS
Column address strobe
/WE
Write Enable
UDQM /LDQM
Data input/output Mask
DQM controls I/O buffers.
DQ0 ~ 15
Data input/output
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD/VSS VDDQ/VSSQ NC
Power supply/Ground Power supply/Ground No connection
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. This pin is recommended to be left No Connection on the device.
Rev.02
4/18
64Mb SDRAM
Block Diagram
A0 A1 A2 A3
Row Add. Buffer
Auto/Self Refresh Counter
DQM
A4
Address Register
A5 A6 A7 A8 A9 A10 A11 BA0 BA1
Row Decoder
Memory Array
Write DQM Control
Data In S/A & I/O gating Col. Decoder Data Out DQi
Col. Add. Buffer
Read DQM Control
Mode Register Set
Col. Add. Counter DQM DQM Burst Counter
Timing Register
CLK
CKE
/CS
/RAS
/CAS
/WE
Rev.02
5/18
64Mb SDRAM
Simplified State Diagram
Self Refresh
LF SE LF SE
it Ex
Mode Register Set
MRS
IDLE
REF
CBR Refresh
CK E CK E
Write
Row Active
ad Re w it
w it h
ACT
Power Down
CKE
BS T Re ad
CKE
Read
Active Power Down
WRITE Suspend
CKE
WRITE
Wr ite
h
Read
READ
Write
CKE CKE
CKE
READ Suspend
PR E
WRITEA Suspend
CKE
WRITEA
E PR
CKE
READA
CKE CKE
READA Suspend
POWER ON
Precharge
Precharge
Manual Input Automatic Sequence
Rev.02
6/18
64Mb SDRAM
Address Input for Mode Register Set
BA1 BA0 A11
A10
A9
A8
A7
A6
A5
A4
A3 BT
A2
A1
A0
Operation Mode
CAS Latency
Burst Length
Sequential 1 2 4 8 Reserved Reserved Reserved Full Page
Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Type Interleave Sequential
A3 0 1
CAS Latency Reserved 2 3 Reserved Reserved Reserved Reserved Reserved
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
BA1 0 0
BA1 0 0
BA0 0 0
A10 0 0
A9 0 1
A8 0 0
A7 0 0
Operation Mode Normal Burst read with Single-bit Write
Rev.02
7/18
64Mb SDRAM
Burst Type ( A3 )
Burst Length 2 A2 A1 A0 XX0 XX1 X0 0 X0 1 X1 0 X1 1 000 001 010 011 100 101 110 111 nnn Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+1 Cn+2 ...... Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 -
4
8
Full Page *
* Page length is a function of I/O organization and column addressing x16 (CA0 ~ CA7) : Full page = 256 bits
Rev.02
8/18
64Mb SDRAM
Truth Table
1. Command Truth Table
Command
Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set
Symbol
DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL MRS
CKE
n-1
H H H H H H H H H H H
n
X X X X X X X X X X X
/CS
H L L L L L L L L L L
/RAS /CAS
X H H H H H L L L L L X H H L L L H H H H L
/WE
X H L H H L H H L L L
BA0, BA1
X X X V V V V V V X L
A10
X X X L H L H V L H L
A11, A9~A0
X X X V V V V V X X V
Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
2. DQM Truth Table
Command
Data w rite / output enable Data mask / output disable Upper byte w rite enable / output enable Read Read w ith auto pre-charge Write Write w ith auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set
Symbol
ENB MASK BSTH READ READA WRIT WRITA ACT PRE PALL MRS
CKE
n-1
H H H H H H H H H H H
n
X X X X X X X X X X X
/CS
H L L L L L L L L L L
Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
3. CKE Truth Table
Command
Activating Any Clock suspend Idle Idle Self refresh Idle Power down
Command
Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Pow er dow n entry Pow er dow n exit
Symbol
CKE
n-1
H L L
n
L L H H L H H L H
/CS
X X X L L L H X X
/RAS /CAS
X X X L L H X X X X X X L L H X X X
/WE Addr.
X X X H H H X X X X X X X X X X X X
REF SELF
H H L L H L
Re m ark H = High level, L = Low level, X = High or Low level (Don't care)
Rev.02
9/18
64Mb SDRAM
4. Operative Command Table
Current state /CS /R
H L L Idle L L L L L H L L Row active L L L L L H L L L Re ad L L L L L H L L L Write L L L L L X H H H L L L L X H H H L L L L X H H H L L L L L X H H H L L L L L
/C /W
X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L
Addr.
X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code
Command
DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Nop or pow er dow n Nop or pow er dow n ILLEGAL ILLEGAL Row activating Nop
Action
Notes
2 2 3 3
Refresh or self refresh Mode register accessing Nop Nop Begin read : Determine AP Begin w rite : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Row active Continue burst to end Row active Burst stop Row active Terminate burst, new read : Determine AP Terminate burst, start w rite : Determine AP ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop Row active Terminate burst, start read : Determine AP 7, 8 Terminate burst, new w rite : Determine AP 7 ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL
4
5 5 3 6 4
7 7, 8 3 4
7,8 7 3 9
Rem ark H = High level, L = Low level, X = High or Low level (Don't care)
Rev.02
10/18
64Mb SDRAM
Current state
/CS /R
H L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L
/C /W
X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code
Command
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Action
Continue burst to end Precharging Continue burst to end Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst to end Write recovering w ith auto precharge Continue burst to end Write recovering w ith auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle af ter tRP Nop Enter idle af ter tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle af ter tRP ILLEGAL ILLEGAL Nop Enter idle af ter tRCD Nop Enter idle af ter tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
3 3 3 3
Re ad w ith AP
L L L L L H L L
Write w ith AP
L L L L L L H L L L
3 3 3 3
3 3 3
Precharging
L L L L L H L L L
3 3 3,10 3
Row activating
L L L L L
Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
Rev.02
11/18
64Mb SDRAM
Current state
/CS /R
H L L L X H H H H L L L L X H H H H L L L L X H H L L X H H H L
/C /W
X H H L L H H L L X H H L L H H L L X H L H L X H H L X X H L H L H L H L X H L H L H L H L X X X X X X H L X X
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X X X X X X X X
Command
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/ BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS
Action
Nop Enter row active af ter tDPL Nop Enter row active af ter tDPL Nop Enter row active af ter tDPL Start read, Determine AP New w rite, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter precharge af ter tDPL Nop Enter precharge af ter tDPL Nop Enter precharge af ter tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRC Nop Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL
Notes
Write re cove ring
L L L L L H L L L L L L L L H L
8 3 3
Write re cove ring w ith AP
3,8 3 3
Re fre shing
L L L H L
M ode Re giste r Acces sing
L L L
Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
Notes 1. All entries assume that CKE w as active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode. All input buffers except CKE w ill be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode. All input buffers except CKE w ill be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. Must mask preceding data w hich don't satisfy tDPL. 10. Illegal if tRRD is not satisfied.
Rev.02
12/18
64Mb SDRAM
5. Command Truth Table for CKE
Current state CKE
n-1 H L Se lf re fre sh L L L L H H H Se lf re fre sh re cove ry H H H H H H Pow er dow n L L H H H H Both banks idle H H H H H H L Row active H L H Any state other than liste d above H L L n X H H H H L H H H H L L L L X H L H H H H H L L L L L X X X H L H L
/CS /R
X H L L L X H L L L H L L L X X X H L L L L H L L L L X X X X X X X X X H H L X X H H L X H H L X X X X H L L L X H L L L X X X X X X X
/C /W
X X H L X X X H L X X H L X X X X X X H L L X X H L L X X X X X X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X X X
Addr.
X X X X X X X X X X X X X X X X X
Action
INVALID, CLK (n - 1) w ould exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) w ould exit pow er dow n Exit pow er dow n Idle Maintain pow er dow n mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table
Notes
X Op-Code
Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table
X Op-Code X X X X X X
Self refresh Refer t o operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend
1 1 1 2
Rem ark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. Self refresh can be entered only from the both banks idle state. Pow er dow n can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Table.
Rev.02
13/18
64Mb SDRAM
Absolute Maximum Ratings
Symbol
VIN, VOUT VDD, VDDQ TOP TSTG PD IOS
Item
Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Current
Rating
-0.3 ~ 4.6 -0.3 ~ 4.6 0 ~ 70 -55 ~ 150 1 50
Units
V V C C W mA
Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended DC Operation Conditions ( Ta = 0 ~ 70 C )
Symbol
VDD VDDQ VIH VIL
Parameter
Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input logic high voltage Input logic low voltage
Min.
3.0 3.0 2.0 -0.3
Typical
3.3 3.3
Max.
3.6 3.6 VDD+0.3 0.8
Units
V V V V
Note : 1. All voltage referred to VSS. 2. VIH (max) = 5.6V for pulse w idth 3ns 3. VIL (min) = -2.0V for pulse w idth 3ns
Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25 C )
Symbol
CCLK CI CO
Parameter
Clock capacitance Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML,DQMU Input/Output capacitance
Min.
2.5 2.5 4.0
Max.
4.0 5.0 6.5
Units
pF pF pF
Rev.02
14/18
64Mb SDRAM
Recommended DC Operating Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 C, Ta = -40 ~ 85 C for 6I/7I)
MAX Parameter Symbol Test condition -55
Burst length = 1, tRC tRC (min), IOL = 0 mA, One bank active CKE VIL (max.), tCk = 15 ns CKE VIL (max.), tCk = CKE VIL (min.), tCK = 15 ns, /CS VIH (min.) Input signals are changed one time during 30ns CKE VIL (min.), tCK = Input signals are stable
Units Notes -6/6I
-7/7L/7I
Operating current Precharge standby current in power down mode
ICC1
95
90
80
mA
1
ICC2P ICC2PS ICC2N
2 1 20
mA mA mA
Precharge standby current in non-power down mode
ICC2NS ICC3P ICC3PS ICC3N
20 7 5 30
mA mA mA mA
Active standby current in power down mode
CKE VIL(m ax), tCK = 15ns CKE VIL(m ax), tCK = CKE VIL(min), tCK = 15ns,/ CS VIH(min) Input signals are changed one time during 30ns CKE VIL(min), tCK = Input signals are stable tCCD = 2CLKs , IOL = 0 mA tRC tRC(min.) CKE 0.2V CL=3 CL=2 130 150
Active standby current in non-power down mode
ICC3NS
35 120 140 1 0.5 110 130
mA
operating current (Burst mode) Refresh current Self Refresh current
ICC4 ICC5 ICC6
mA mA mA
2 3 4 5
Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 3. Input signals are changed only one time during tCK(min) 4. Standard pow er version. 5. Low pow er version.
Rev.02
15/18
64Mb SDRAM
Recommended DC Operating Conditions ( Continued )
Parameter Symbol Test condition Min. Max. Unit
Input leakage current
IIL
0 VI VDDQ, VDDQ=VDD All other pins not under test=0 V
-0.5
+0.5
uA
Output leakage current High level output voltage Low level output voltage
IOL VOH VOL
0 VO VDDQ, DOUT is disabled Io = -4mA Io = +4mA
-0.5 2.4
+0.5
uA V
0.4
V
AC Operating Test Conditions
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70C )
Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level
1.4V / 1.4V See diagram as below 2.4V / 0.4V 2ns 1.4V
Vtt = 1.4V 50
Output
Z = 50 50pF
Rev.02
16/18
64Mb SDRAM
Operating AC Characteristics
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 C, Ta = -40 ~ 85 C for 6I/7I)
-55 Min.
5.5 tCK 7.5 5.2 6 tCH tCL CL = 3 Data-out hold time CL = 2 CL = 3 Data-out high impedance time Data-out low impedance time Input hold time Input setup time ACTIVE to ACTIVE command period ACTIVE to PRECHARGE command period PRECHARGE to ACTIVE command period ACTIVE to READ/WRITE delay time ACTIVE(one) to ACTIVE(another) command READ/WRITE command to READ/WRITE command Data-in to PRECHARGE command Data-in to BURST stop command Data-out to high impedance from PRECHARGE command Refresh time(4,096 cycle) All voltages referenced to Vss. Note : 1. tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number) CL = 3 CL = 2 tREF 64 64 CL = 2 tLZ tIH tIS tRC tRAS tRP tRCD tRRD tCCD tWR tBDL tROH 0 1 1.5 55 40 18 18 12 1 2 1 3 100k 0 1 2 60 42 18 18 14 1 2 1 3 100k 1 1 1 2 63 42 18 18 16 1 2 1 3 2 64 100k tHZ 2 5 2.5 5 tOH 2.3 2.3 2.2 2.5 2.5 2.5
Parameter
CL = 3 Clock cycle time CL = 2 CL = 3 Access time from CLK CLK high level width CLK low level width CL = 2
Symbol
-6/6I
Min. 6 7.5 5.5 6 3 3 Max.
-7/7L/7I
Min. 7 7.5 6 6 Max.
Max.
Units Notes ns ns ns ns ns ns ns ns
tAC
2.5 2.5 6 6
ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK CLK ms 2 2 2 2 2
Rev.02
17/18
64Mb SDRAM
Package Dimension
Rev.02
18/18

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